1. Field of the Invention
The present invention lies within the field of computer chip design. More particularly, it relates to an electronic computing circuit for implementing a method for reducing the bit width of two operands from a bit length N to a reduced bit length M, thus, M<N.
2. Description and Disadvantages of Prior Art
Above methods are frequently used in prior art saturation arithmetics, wherein a plurality of operands having a standard bit width of e.g. 32 bit are added. In these cases, intermediate results exist having a bit width of more than 32 bit, for example of 35 bit. Prior art saturation arithmetic usually first reduces the plurality of 32 bit input operands to two operands of such increased bit width (35 bit), and then adds the 35 bit operands in a particular 35 bit adder device. Such adder device adds up the two operands and saturates the result to a bit length which is again smaller than that of the input operands and which mostly corresponds to a standard bit length like e.g. 32 bit. An example of a saturated adder device is disclosed in the European patent application no. 0,209,014 B1. A disadvantage of the procedure disclosed there is that an adder device must be used which is adapted to process input operands having a bit length of other than a power of two. In the example above this was 35. Although this is not a severe problem to construct a 35 bit adder, such adder unit needs to be designed and must be optimised for speed, for space and for the special operand type in use. This especially applies for so-called single-instruction-multiple-data (SIMD) operations. The data width in these units is variable and depends on the instruction in use. The common widths are by the power of two, like 8, 16, 32, 64 etc. Operands and results are always of this width.
The usual prior art approach is to accept the complexity of the operands having a bit length exceeding the powers of two and to build for each individual bit width building blocks on a chip which are capable to operate with the locally required operand widths resulting in many such building blocks. This is sketched in FIG. 1.
With special reference to FIG. 1 a schematic block diagram representation of a prior art chip design architecture is shown processing a “Sum across Instruction” having five 32 bit input operands 10, including a prior art 3:2 compression stage 12 and a subsequent 4:2 compression stage 14, which generates two output operands of each 35 bit. These 35-bit operands are then added in a circuit 16 in order to yield a 32-bit add result. Circuit 16 is shown to comprise a 35 bit vector merging adder 17 (VMA) as input stage, which adds up the two operands from stage 14. A 35-bit sum and the carry of the most significant bit are output from unit 17 to a saturation circuit 19, which calculates a 32-bit saturated add result based on the carry bit and the 35-bit sum.
By that the additional complexity and very heterogeneous micro architecture of such a design is accepted, which tends to render the resulting chip structure quite complex. In addition, this prior art approach disables a wider re-usage of existing designs or building blocks being all specialised to the usual bit length of a power of 2 (8, 16, 32, 64 etc.), the chip structure of which is already highly optimised in regard of speed and space savings.